Traditional display interfaces such as VGA, DVI, HDMI, LVDS require a dedicated clock generation circuit for each simultaneously active output connected to a source device such as a PC or GPU. The relatively high cost of implementing several of these clock source circuits has been one factor that has limited the total number of simultaneous displays that could be driven at a time by a single GPU.
It is known to drive multiple displays at a time with a shared clock synthesis circuit using a reference clock such as a crystal, only if all these displays use the exact same timing (e.g., resolution, refresh rate and pixel clock rate). However, in many applications, the multiple displays may not have the same exact timing. For example, a consumer may have one type of display that operates using one timing scheme and another display that operates at a different timing scheme. In this example, the two monitors could not be driven using a shared clock synthesis circuit because they both don't have the exact same timing scheme. Therefore, in this example, a dedicated clock generation circuit is required for each of the displays.
Accordingly, a need exists for a method and apparatus that requires less clock source circuits than known source devices and has the capability drive multiple displays that operate using different timing schemes.